The present invention relates to art of electronic packaging, and more specifically to assemblies incorporating microelectronic components.
Modern electronic devices utilize integrated circuits, commonly referred to as xe2x80x9csemiconductor chipsxe2x80x9d which incorporate numerous electronic elements. These chips are mounted on substrates that physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a printed circuit board or card, or part of a discrete chip package, such as a single chip package (which is also referred to as a semiconductor chip package) or multi-chip package. The chip package is typically incorporated into a larger circuit by being mounted on a printed circuit board. An interconnection between the chip and the chip package is commonly referred to as a xe2x80x9cfirst levelxe2x80x9d assembly or chip interconnection. An interconnection between the chip package and a printed circuit board or card is commonly referred to as a xe2x80x9csecond levelxe2x80x9d interconnection. If the chip is mounted directly on a printed circuit board, the interconnection between the bare chip and the board is intermediate between a first and second level interconnection.
The structures utilized to provide the first level connection between the chip and the substrate of the chip package must accommodate all of the required electrical interconnection to the chip. The center to center distance between one I/O and an adjacent I/O is typically referred to as the pitch. As chip technology advances, the number of first level connections to external circuit elements, commonly referred to as xe2x80x9cinput-outputxe2x80x9d or xe2x80x9cI/Oxe2x80x9d connections per chip tends to increase. If the size of the chip remains constant then the pitch must be smaller to accommodate the increased number of I/O""s in the same area. Advances in chip technology, however, frequently also allow the production of smaller chips having the same or a greater degree of functionality. Generally, as the chip size decreases and the number of chip contacts increase, the pitch of the second level interconnections becomes smaller and smaller. For example it is not uncommon for chip scale packages, such as the packages disclosed in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266 to have a terminal pitch of 750 xcexcm or less.
In order to make a second level interconnection between a semiconductor chip package having closely spaced I/O""s and a printed circuit board, the pitch of the I/O""s of the package and the pitch of the connection pads on the printed circuit board must be the same. If they are different the I/O""s will not align with the connection pads, and the package and the board will not be electrically interconnected. When a package having terminals in the form of a pin grid array (xe2x80x9cPGAxe2x80x9d) is plugged into a printed circuit board, the apertures on the board must be aligned with and have the same pitch as the pins of the PGA. The same is true of ball grid arrays (xe2x80x9cBGA""s), where the solder balls of the BGA must be aligned with connection pads on the printed circuit board and with flip chip die where the solder bumps on the bare die must be aligned with connection pads on the printed circuit board. The pitch of many chip scale packages and of some conventional semiconductor chip packages is smaller than the pitch of standard printed circuit boards. For example, printed circuit boards made from FR-4 having connection pads with a pitch of 1000 xcexcm or more are commonly available. If a smaller pitch is needed, the printed circuit board must typically be made of a more esoteric, and expensive material, such as BT resin. It is desirable to have the ability to mount a packages having a small pitch to a standard low cost printed circuit board having a larger pitch.
Even if the availability of lower cost printed circuit boards with small pitches should increase, there is still a need to be able to connect a package having one pitch with a printed circuit board having another pitch. This ability is desirable when one of the components to be mounted to a printed circuit board has a pitch which is different from the pitch of the other components and of the board. Such a situation might occur with high volume components that are most affordable in a particular pitch or with low volume components which may only be available in a limited number of configurations. The semiconductor chip package and translator of the present invention allows a package with one pitch to be mounted to a board having a different pitch.
In addition, it is also desirable to manufacture semiconductor chip packages in wafer level process. A wafer level process can provide significant advantages in handling and process chips. However, wafer-level processing is not normally used to form fan-out or fan-in/fan-out structures. A wafer level package having a fan-out structure will intrinsically be larger than its silicon die and would therefor waste silicon and reduce the number of die per wafer. These economic concerns usually rule out wafer level packaging processes that are larger than the chip.
The present invention relates to an electronic assembly which includes a semiconductor chip package and a translator. The translator is used to step up or step down the pitch of the package to match the pitch of the printed circuit board or external substrate to which the package is to be mounted. The semiconductor chip package includes a semiconductor chip and an array of electrically conductive terminals disposed on the face surface of the package. In preferred embodiments, the semiconductor chip package is selected from the packages described in commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,518,964; 5,685,885; and 5,668,885, the disclosures of which are incorporated herein by reference. The translator includes a flexible, sheet-like support element having an array of electrically conductive terminals (hereinafter xe2x80x9cfirst translator terminalsxe2x80x9d). This array of first translator terminals has a pitch which corresponds to the pitch of the semiconductor chip package. Typically, this array is located on a central region of the support element and the first terminals are exposed to the surface of the support element which faces the package. The translator also has a second array of electrically conductive terminals (hereinafter xe2x80x9csecond translator terminalsxe2x80x9d) disposed on the support element and exposed on the second surface of the translator. If the translator is used to connect a package have a small pitch to a printed circuit board having a larger pitch, at least some of the second translator terminals will be disposed on the peripheral region of the support element.
The support element of the translator should be made of a flexible material, such as polyimide. Since the footprint of the translator will typically be larger than the footprint of the semiconductor chip package, it may be necessary for the region of the translator which extends beyond the edges of the semiconductor chip package to have additional structural integrity. This is typically done by making the peripheral region of the support element more rigid, such as, for example by incorporating a stiffener, such as a ring of plastic, metal or other rigid material, into the support element.
The pitch of the array of first translator terminals is the same as the pitch of the semiconductor chip package. The pitch of the array of second translator terminals is the same as the pitch the printed circuit bard, or other external substrate to which the assembly will be mounted. The package can be mounted on the board by using a translator having a pitch on a first surface corresponding to the pitch of the package and a pitch on a second surface corresponding to the pitch of the board. The translator of the electronic assembly of the present invention present may also function as a socket such as the components described in commonly assigned U.S. Pat. Nos. 5,615,824; and 5,632,631; and commonly assigned U.S. patent application Ser. No. 08/254,991, filed on Jun. 7, 1994; and 08/862,151, filed on May 22, 1997, the disclosures of which are incorporated herein by reference. When functioning as such a component, the translator may include, as described in the ""991 patent application, a plurality of holes which are aligned in an array corresponding to the array of package terminals. Each of the first translator terminals is disposed over one of the holes is functions as a resilient, generally laminar contact that extends inwardly over the hole and is adapted to resiliently engage a package terminal.
The translator of the electronic assembly of the present invention may also be used to route one or more signals from one portion of the package to another by, for example, incorporating a trace which interconnects one package terminal to a different package terminal.
The present invention also relates to a method of making a electronic assembly. The method includes the steps of providing a semiconductor chip package having an array of package terminals and a translator. The translator has an array of first translator terminals with a pitch which corresponds to the pitch of the semiconductor chip package. The translator also has a array of second translator terminals with a pitch which corresponds to the pitch of the substrate to which the semiconductor chip is to be mounted. The package and translator are juxtaposed, such that the package terminals and the first translator terminals are aligned, and bonded together. The semiconductor chip package of the present invention may include leads connecting the semiconductor chip to a dielectric layer. The semiconductor chip package may be made in a wafer level process wherein a subassembly incorporating many chips is formed on a wafer. The chips are then severed from the wafer subassembly to from a plurality of semiconductor chip packages, each incorporating a chip, a dielectric layer and leads. A wafer level process, such as the process described in U.S. Pat. No. 5,518,964, provides significant advantages in handling and process chips, such as the ability to process numerous chips which many contacts and provide packages with a large number of terminals on a small pitch. Such packages may be mounted on external substrates having pitches which differ from the small pitch of the package by juxtaposing and bonding a translator having a first pitch which matches the package pitch and a second pitch which matches the external substrate pitch.